Electronic signaling within and between integrated circuits (ICs) is accomplished using many different formats, standards, and approaches. Each of these electronic signaling types may be based on and/or reflect a voltage range or swings thereof, an absolute current or changes thereto, a signaling speed or frequency modulation, a combination thereof, and so forth. The various circuits that are used to implement such different electronic signaling types are equally diverse.
Two examples of such diverse circuit types for implementing the different electronic signaling types are (i) Positive-Referenced Emitter Coupled Logic (PECL) circuitry and (ii) Peripheral Control Interface (PCI) Express circuitry. These two circuit types may be employed as, for example, signal input receivers.
FIG. 1 illustrates a conventional signal input receiver that may be PECL-compliant. In a described implementation, FIG. 1 is divided into two general regions: an off chip region and an on chip region, with the on chip region representing an IC chip. The demarcation between these two regions is indicated by dashed lines. The on chip region includes a sampler 101 that is adapted to recover data from signals that are received from the off chip region.
The off chip region includes two inputs INP and INN. These inputs may represent a positive input (INP) and a negative input (INN) for a two-line signaling format such as differential signaling. The off chip region is alternating current (AC) coupled to the on chip region via an AC coupling capacitance as represented by capacitors 103P and 103N.
Via capacitors 103P and 103N, incoming signals are provided to the chip at a positive receiver termination (RTP) node and a negative receiver termination (RTN) node. Depending on the context herein, node labels such as “RTP” and “RTN” may represent a physical node of a circuit, a voltage level at the node, signals present at and/or propagating through the node, an input and/or output, some combination thereof, and so forth.
A resistor 105 is coupled between nodes RTP and RTN. The resistance value of resistor 105 is equal to two times the termination resistance (designated “RTERM”) that is used to terminate a link that is represented by the lines for nodes INP and INN. The individual termination resistances are set equal to the impedance of the link to reduce, if not minimize, signal reflections that arise from mismatched impedances. For example, the resistance value of resistor 105 may be set to match twice an individual trace impedance of a printed circuit board (PCB) to which the IC chip is coupled.
A resistor 107P1 is connected in series with a resistor 107P2. Specifically, resistor 107P1 is coupled between a supply voltage VDD and node RTP, and resistor 107P2 is coupled between node RTP and a ground potential. Resistors 107P1 and 107P2 therefore form a voltage divider 107P that can set a DC voltage level for node RTP in conjunction with supply voltage VDD. In other words, for voltage divider 107P, the ratio of the resistance value of resistor 107P1 to the sum of the resistance values of resistors 107P1 and 107P2 sets the DC voltage level at node RTP as a percentage of supply voltage VDD.
Similarly, resistor 107N1 is connected in series with a resistor 107N2. Specifically, resistor 107N1 is coupled between supply voltage VDD and node RTN, and resistor 107N2 is coupled between node RTN and the ground potential. Resistors 107N1 and 107N2 therefore form a voltage divider 107N that can set a DC voltage level for node RTN in conjunction with supply voltage VDD.
Nodes RTP and RTN are input to sampler 101 so that the sampler circuitry thereof may recover the data encoded into the differential signals that are present at nodes RTP and RTN. A common mode voltage for the RTP and RTN inputs into sampler 101 may be established using the voltage dividers 107P and 107N that are created by resistors 107P1, 107P2 and 107N1, 107N2, respectively.
With off-chip AC coupling via capacitors 103P and 103N, the common mode voltage of nodes RTP and RTN can be set to a desired voltage level regardless of the incoming common mode voltage of nodes INP and INN by using voltage dividers 107P and 107N. The common mode voltage of nodes RTP and RTN is typically set to a voltage level that optimizes the input sensitivity of sampler 101 and that allows a desired voltage swing at nodes RTP and RTN without turning on an electrostatic discharge (ESD)-protection diode, especially in a low supply voltage VDD environment.
As noted above, the conventional signal input receiver of FIG. 1 may be PECL-compliant. For example, such a signal input receiver may be used in a device that comports with a given PECL standard. However, it should be understood that other circuitry may also be involved to fully realize a complete device that comports with the given PECL standard.
For PECL signaling on a high-speed serial link for example, a high voltage swing is typically employed. Also, sampler 101 is typically designed with transistors that do not perform well at input common mode voltages near, much less below, zero volts. Consequently, the common mode voltage set by voltage dividers 107P and 107N is typically far above zero volts. However, for PCI Express signaling, the signal input receiver is specified to have a zero volt termination.
In other words for PCI Express signaling, the signal common mode voltage on the chip side of the AC coupling capacitors 103P and 103N (i.e., the common mode voltage at nodes RTP and RTN) is to be maintained at zero volts. The signal input receiver of FIG. 1 therefore fails to meet the specifications for PCI Express. Moreover as noted above, even if nodes RTP and RTN were forced to zero volts, samplers 101 tend not to operate in an optimum fashion with common mode voltages that are not at a sufficiently positive level.
Regardless, the conventional signal input receiver of FIG. 1 as illustrated has inputs to the IC chip that have a common mode voltage that is equal to that of the inputs to sampler 101. However, the common mode voltage of the inputs to the IC chip may be separated from the common mode voltage of the inputs to sampler 101, as illustrated in FIG. 2.
FIG. 2 illustrates a conventional signal input receiver that may be PCI Express-compliant and/or PECL compliant. The circuitry of FIG. 2 is similar to the circuitry of FIG. 1. However, the conventional signal input receiver of FIG. 2 is illustrated with inputs to the IC chip that have a common mode voltage that is not equal to that of the inputs of sampler 101.
One notable component-level difference is the addition of on-chip capacitance as implemented by capacitors 203P and 203N. Capacitor 203P and capacitor 203N are coupled between nodes RTP and RDP and nodes RTN and RDN, respectively. The impact of capacitors 203P and 203N, as well as the presence of nodes RDP and RDN, is described further below.
As in FIG. 1, the input signals INP and INN that are arriving at the on chip region from the off chip region are provided via the AC coupling capacitance as represented by capacitors 103P and 103N, respectively. The input signals on line INP and line INN are terminated at node RTP and node RTN using a resistor 201P and a resistor 201N, respectively. Each resistance value for resistors 201P and 201N is set equal to “RTERM”, a resistance value that equals the impedance of a respective input line INP and INN.
Sampler 101 of FIG. 2 also recovers data that is encoded into signaling such as the differential signaling that is initially received at nodes RTP and RTN. Resistors 107P1 and 107P2 and resistors 107N1 and 107N2 function to divide supply voltage VDD into two parts as separated by the input nodes RDP and RDN, respectively, of sampler 101.
However, these input nodes RDP and RDN of sampler 101 no longer correspond to the on chip input nodes RTP and RTN from a DC perspective because of capacitors 203P and 203N. Instead, node “RDP” corresponds to a positive receiver node that is decoupled from node RTP from a DC perspective because of the effects of capacitor 203P. Node “RDN” corresponds to a negative receiver node that is decoupled from node RTN from a DC perspective because of the effects of capacitor 203N.
Thus, capacitors 203P and 203N impact the on chip circuitry of FIG. 2 by creating an AC-coupling between nodes RTP and RDP and between nodes RTN and RDN. This AC coupling enables the on chip circuitry to provide ground-terminated inputs to the off-chip signaling in order to meet the specifications of PCI Express. Moreover, the AC decoupling created by capacitors 203P and 203N permits use of voltage dividers 107P and 107N in order to set a common mode voltage for the inputs of sampler 101 that is above ground. This improves the sensitivity of sampler 101.
Unfortunately, there are drawbacks to using the on-chip capacitance as implemented with capacitors 203P and 203N. In order to ensure that a long string of “1s” or “0s” is not degraded, the value of the on-chip capacitors is relatively large. For example, if the resistance value of resistor 107P1 in parallel with resistor 107P2 (and resistor 107N1 in parallel with resistor 107N2) is typically equal to a few kilo-ohms, then the capacitance value of capacitor 203P (and capacitor 203N) is equal to a few hundred pico-farads. The consequences to this drawback are described further below with regard to two possible approaches for creating capacitors 203P and 203N.
These two possible approaches are (i) using a transistor that is operating as a capacitor and (ii) using a metal capacitor built directly on the IC chip. In the first approach, capacitors 203P and 203N are created using an active device such as a metal oxide semiconductor (MOS) transistor. Unfortunately, not only does each such transistor occupy a large surface area of the IC chip, but this approach places another constraint on sampler 101. Specifically, the common mode voltage of nodes RDP and RDN is limited to ensure that the transistor is fully turned on.
In the second approach, capacitors 203P and 203N are created using two metal layers that are separated by some dielectric. In other words, capacitors 203P and 203N may be created using a “metal cap”. Unfortunately, because the capacitance value of such capacitors is equal to a few hundred pico-farads, the dielectric is thick relative to a gate oxide thickness of the first (transistor) approach and the surface area of each such metal cap is quite large. This surface area is even larger than that required for active devices because metal caps have a lower capacitance per unit area. The large surface area that is consumed by either a metal cap or a transistor is undesirable because it adds to the size and thus the cost of an IC chip.
Moreover, with either approach, because nodes RDP and RDN are not accessible off chip, no DC test of sampler 101 may be performed. Furthermore, problems can develop with large swings of the INP and INN signals. For example, PECL-compliant signals have a maximum input voltage swing of 2.6 volts peak-to-peak. If the input signals RTP and RTN undergo a 2.6 volt peak-to-peak swing about a ground termination level, the input signal may plunge sufficiently below zero volts so as to turn on the ESD-protection diode.
Thus, there is no existing approach for combining a PCI Express-compliant signal input receiver and a PECL-compliant signal input receiver. Accordingly, there is a need for methods and apparatuses for implementing a multi-mode signal input receiver, including schemes and techniques that enable such a multi-mode signal input receiver to reproduce respective characteristics of the different signal input receivers for the respective individual modes.
Furthermore, there is no existing approach for efficiently integrating into a signal input receiver both (i) PCI Express-compliant inputs that are ground terminated and (ii) a typical sampler that is more sensitive with a positive common mode voltage input. Accordingly, there is a need for methods and apparatuses for implementing a signal input receiver in which PCI Express-compliant inputs are efficiently and operationally integrated with a typical sampler without sacrificing the input sensitivity thereof.